1. Field of the Invention
The present invention relates to an STM mapping circuit that performs a mapping process for storing packet data in the payload of STS (Synchronous Transport Signal) frames or STM (Synchronous Transfer Module) frames while distributing the packet data to prescribed logic channels.
2. Description of the Related Art
In recent years, the transmission bit rate of communication lines has been increasing to meet the demand for increase in the amount of traffic in information communication. However, the transmission bit rate is limited by the signal processing speed of transmission devices, i.e., factors such as the processing speed of LSI and the inter-device data transfer speed, and methods have therefore been adopted for handling higher speeds by processing after expanding a received signal into parallel signals. For example, when a signal is received from a communication line having a transmission bit rate of 2.488 Gbps, the signals can be handled with sufficient processing speed if the received signal is parallel-expanded to 64 38.88-Mbps signals.
When processing variable-length packets in which the data length varies with each packet as in PPP (Point-to-Point Protocol), the variable-length packets are typically broken up into small packets of fixed length such as ATM (Asynchronous Transfer Mode) cells which then undergo switching in transmission devices. In recent years, however, methods have been proposed for handling variable-length packets as-is without breaking them into fixed-length packets by means of standardized work such as T1×1. GFP (Generic Framing Procedure) and SDL (Simple Data Link) are known as communication methods that carry out this type of processing.
In the above-described GFP and SDL, pad bytes are inserted between variable-length packets, and the length of each packet is converted to a length that is an integer power of the number of parallel-expanded signals. Pad bytes are constituted by a predetermined pattern in which “0” and “1” are repeated, or by a pattern of all “0”, and the pad byte itself has no logical significance.
Signal sequences in which such pad bytes are inserted are shown in FIG. 1A and FIG. 1B.
FIG. 1A and FIG. 1B show examples of signal sequences that are processed in a transmission device, FIG. 1A being a schematic diagram of an example of a signal sequence in which pad bytes have been inserted, and FIG. 1B being a schematic diagram showing an example of a signal sequence in which there are no pad bytes.
FIG. 1A is an example in which packet data have been parallel-expanded into eight bytes (from byte 0 to byte 7). Data sequence A that is shown in FIG. 1A is a packet of a total of 10 bytes from byte data A-1 to A-10, six pad bytes being inserted between byte data A-10 and the next data sequence B. Similarly, data sequence B is a packet of a total of 14 bytes from byte data B-1 to B-14, two pad bytes being inserted between byte data B-14 and the next data sequence C. Data sequence C is a packet of a total of 12 bytes from byte data C-1 to C-12, four pad bytes being inserted between byte data C-12 and the next data sequence D.
When pad bytes of a prescribed number are inserted between each of variable-length packets in this way, the leading byte data of each packet can each be stored in the leading byte of the parallel-expanded signal sequence (Byte 0 in FIG. 1A), thereby making the head of each packet obvious and facilitating subsequent processing.
For example, when a predetermined fixed-length bit pattern is inserted at the head of a packet, the bit pattern can be easily detected by monitoring Byte 0. In addition, processing such as switching is facilitated because data of a plurality of packets are not contained within the data of a plurality of bytes (Bytes 0–7 in FIG. 1A) that are processed all at once by means of parallel expansion.
Nevertheless, when packets that contain pad bytes are outputted from a transmission device to a communication line, the pad bytes are unnecessary data that take up more of the line bandwidth than is necessary and are therefore preferably eliminated as shown in FIG. 1B.
FIG. 1B shows the state of a signal sequence in which the pad bytes shown in FIG. 1A have been eliminated and byte data B-1 of data sequence B are inserted after byte data A-10 of data sequence A. Similarly, data C-1 of data sequence C are inserted after data B-14 of data sequence B, and data D-1 of data sequence D are inserted after data C-12 of data sequence C.
As a means of eliminating the pad bytes, a method can be considered in which, for example, each item of packet data that contains pad bytes is first stored in memory, and then, after determining whether each item of data is effective data or pad bytes, extracting only the effective data.
However, the communication method in which processing is performed after inserting pad bytes between variable-length packets is a new technique that has only recently been proposed, and no proposals have been made regarding a specific method of eliminating pad bytes.
Nevertheless, STM/Packet hybrid switches have been developed in recent years for performing switching of packets of PPP (Point-to-Point Protocol) or the transmission frames of STM format, which is a multiplexed format, in SDH (Synchronous Digital Hierarchy), but these devices necessitate processing to eliminate the above-described pad bytes. As a result, STM mapping circuits that are equipped in the above-described STM/Packet hybrid switches for mapping byte data to the payload areas of transmission frames are preferably provided with the capacity to eliminate pad bytes.
When storing units of AU (Administrative Unit)-3 or AU-4 in the payload areas of the transmission frames of STS (Synchronous Transport Signal)-n and STM (Synchronous Transfer Module)-n, the processing units are referred to as “channels.” This type of channel is hereinbelow referred to as a “physical channel,” and packet classifications that are distinguished for each destination by means of the header portions of variable-length packets are hereinbelow referred to as “logical channels.”